Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n + 4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-ANDEXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-ANDEXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 ≤ r ≤ n). We show that only (r + n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network. key words: logic synthesis, exclusive-or, single stuck-at fault, easily testable realization